PC912XDP512F0CFVR datasheet(1027/1348 Pages) FREESCALE

1027 / 1348 page

24.0.6

Registers

24.0.6.1

Data Register

This register holds the value driven out to the pin if the pin is used as a general purpose I/O.

Writing to this register has only an effect on the pin if the pin is used as general purpose output.

When reading this address, the buffered state of the pin is returned if the associated data direction

If the data direction register bits are set to logic level “1”, the contents of the data register is

returned. This is independent of any other configuration (Figure 24-68).

24.0.6.2

Input Register

This is a read-only register and always returns the buffered state of the pin (Figure 24-68).

24.0.6.3

Data Direction Register

This register defines whether the pin is used as an input or an output.

If a peripheral module controls the pin the contents of the data direction register is ignored

(Figure 24-68).

Figure 24-68. Illustration of I/O Pin Functionality

yes

—

yes

AD1

yes

—

yes

—

1. Each cell represents one register with individual conﬁguration bits

Table 24-60. Register Availability per Port1

Port

Data

Direction

Input

Reduced

Drive

Pull

Enable

Polarity

Select

Wired-OR

Mode

Interrupt

Enable

Interrupt

Flag

DDR

output enable

module enable

PTI

data out

Module

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