PC912XDP512F0CFVR datasheet(693/1348 Pages) FREESCALE

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Chapter 19 S12X Debug (S12XDBGV2) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

695

XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE

module. When the CPU enters active BDM mode through a BACKGROUND command, with the DBG

module armed, the DBG remains armed.

The DBG module tracing is disabled if the MCU is secure. Breakpoints can however still be generated if

the MCU is secure.

19.1.4

Block Diagram

Figure 19-1 shows a block diagram of the debug module.

Figure 19-1. Debug Block Diagram

19.2

External Signal Description

The DBG sub-module features two external tag input signals (see Table 19-2). See Device User Guide

(DUG) for the mapping of these signals to device pins. These tag pins may be used for the external tagging

in emulation modes only

Table 19-1. Mode Dependent Restriction Summary

BDM

Enable

BDM

Active

MCU

Secure

Comparator Matches

Enabled

Breakpoints

Possible

Tagging

Possible

Tracing

Possible

Yes

Only SWI

Yes

Active BDM not possible when not enabled

Yes

XGATE only

CPU BUS

TRIGGER

EXTERNAL TAGHI / TAGLO

MATCH0

XGATE BUS

COMPARATOR B

COMPARATOR C

COMPARATOR D

COMPARATOR A

MATCH1

MATCH2

MATCH3

READ TRACE DATA (DBG READ DATA BUS)

SECURE

BREAKPOINT REQUESTS

XGATE S/W BREAKPOINT REQUEST

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