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PC912XDP512F0CFVR bảng dữ liệu(PDF) 686 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0CFVR bảng dữ liệu(HTML) 686 Page - Freescale Semiconductor, Inc |
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686 / 1348 page ![]() Chapter 18 Memory Mapping Control (S12XMMCV3) MC9S12XDP512 Data Sheet, Rev. 2.21 686 Freescale Semiconductor 18.5.3 On-Chip ROM Control The MCU offers two modes to support emulation. In the first mode (called generator) the emulator provides the data instead of the internal FLASH and traces the CPU actions. In the other mode (called observer) the internal FLASH provides the data and all internal actions are made visible to the emulator. 18.5.3.1 ROM Control in Single-Chip Modes In single-chip modes the MCU has no external bus. All memory accesses and program fetches are internal (see Figure 18-27). Figure 18-27. ROM in Single Chip Modes 18.5.3.2 ROM Control in Emulation Single-Chip Mode In emulation single-chip mode the external bus is connected to the emulator. If the EROMON bit is set, the internal FLASH provides the data and the emulator can observe all internal CPU actions on the external bus. If the EROMON bit is cleared, the emulator provides the data (generator) and traces the all CPU actions (see Figure 18-28). Figure 18-28. ROM in Emulation Single-Chip Mode MCU Flash No External Bus EROMON = 1 Emulator MCU EROMON = 0 Emulator Flash MCU Flash Observer Generator |
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