PC912XDP512F0CFVR datasheet(669/1348 Pages) FREESCALE

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Chapter 18 Memory Mapping Control (S12XMMCV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

669

18.3.2.10 RAM XGATE Upper Boundary Register (RAMXGU)

Read: Anytime

Write: Anytime when RWPE = 0

18.3.2.11 RAM Shared Region Lower Boundary Register (RAMSHL)

Read: Anytime

Write: Anytime when RWPE = 0

Address: 0x011D

76543210

XGU6

XGU5

XGU4

XGU3

XGU2

XGU1

XGU0

Reset

11111111

= Unimplemented or Reserved

Figure 18-18. RAM XGATE Upper Boundary Register (RAMXGU)

Table 18-16. RAMXGU Field Descriptions

Field

Description

6–0

XGU[6:0]

XGATE Region Upper Boundary Bits 6-0 — These bits deﬁne the upper boundary of the RAM region allocated

to the XGATE module in multiples of 256 bytes. The 256 byte block selected by this register is included in the

region. See Figure 18-25 for details.

Address: 0x011E

76543210

SHL6

SHL5

SHL4

SHL3

SHL2

SHL1

SHL0

Reset

11111111

= Unimplemented or Reserved

Figure 18-19. RAM Shared Region Lower Boundary Register (RAMSHL)

Table 18-17. RAMSHL Field Descriptions

Field

Description

6–0

SHL[6:0]

RAM Shared Region Lower Boundary Bits 6–0 — These bits deﬁne the lower boundary of the shared memory

region in multiples of 256 bytes. The block selected by this register is included in the region. See Figure 18-25

for details.

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