PC912XDP512F0CFVR datasheet(534/1348 Pages) FREESCALE

534 / 1348 page

Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

534

Freescale Semiconductor

Figure 12-12. SPI Clock Format 1 (CPHA = 1)

The SS line can remain active low between successive transfers (can be tied low at all times). This format

is sometimes preferred in systems having a single ﬁxed master and a single slave that drive the MISO data

line.

•

Back-to-back transfers in master mode

In master mode, if a transmission has completed and a new data byte is available in the SPI data

The SPI interrupt request ﬂag (SPIF) is common to both the master and slave modes. SPIF gets set one

half SCK cycle after the last SCK edge.

for tT, tl, tL

Minimum 1/2 SCK

Begin

End

SCK (CPOL = 0)

SAMPLE I

CHANGE O

SEL SS (O)

Transfer

SCK (CPOL = 1)

MSB ﬁrst (LSBFE = 0):

LSB ﬁrst (LSBFE = 1):

MSB

LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

CHANGE O

SEL SS (I)

MOSI pin

MISO pin

Master only

MOSI/MISO

tL = Minimum leading time before the ﬁrst SCK edge, not required for back-to-back transfers

tT = Minimum trailing time after the last SCK edge

tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers

13 14

SCK Edge Number

End of Idle State

Begin of Idle State

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