PC912XDP512F0CFVR datasheet(450/1348 Pages) FREESCALE

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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

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Freescale Semiconductor

Read: For transmit buffers, anytime when TXEx ﬂag is set (see Section 10.3.2.7, “MSCAN Transmitter

Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see

Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers,

only when RXF ﬂag is set (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”).

Write: For transmit buffers, anytime when TXEx ﬂag is set (see Section 10.3.2.7, “MSCAN Transmitter

Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see

Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for

receive buffers.

Reset: Undeﬁned (0x00XX) because of RAM-based implementation

10.3.3.1

Identiﬁer Registers (IDR0–IDR3)

The identiﬁer registers for an extended format identiﬁer consist of a total of 32 bits; ID[28:0], SRR, IDE,

and RTR bits. The identiﬁer registers for a standard format identiﬁer consist of a total of 13 bits; ID[10:0],

RTR, and IDE bits.

10.3.3.1.1

IDR0–IDR3 for Extended Identiﬁer Mapping

Figure 10-25. Receive/Transmit Message Buffer — Standard Identiﬁer Mapping

Name

Bit 7

654321

Bit 0

IDR0

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

IDR1

ID2

ID1

ID0

RTR

IDE (=0)

IDR2

IDR3

= Unused, always read ‘x’

76543210

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

Reset:

xxxxxxxx

Figure 10-26. Identiﬁer Register 0 (IDR0) — Extended Identiﬁer Mapping

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