PC912XDP512F0CFVR datasheet(430/1348 Pages) FREESCALE

430 / 1348 page

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

430

Freescale Semiconductor

The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time

quanta (Tq) clock cycles per bit (as shown in Table 10-7 and Table 10-8).

Eqn. 10-1

10.3.2.5

MSCAN Receiver Flag Register (CANRFLG)

A ﬂag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition

which caused the setting is no longer valid. Every ﬂag has an associated interrupt enable bit in the

CANRIER register.

Table 10-7. Time Segment 2 Values

TSEG22

TSEG21

TSEG20

Time Segment 2

1 Tq clock cycle1

1 This setting is not valid. Please refer to Table 10-35 for valid settings.

2 Tq clock cycles

:::

7 Tq clock cycles

8 Tq clock cycles

Table 10-8. Time Segment 1 Values

TSEG13

TSEG12

TSEG11

TSEG10

Time segment 1

1 Tq clock cycle1

1 This setting is not valid. Please refer to Table 10-35 for valid settings.

2 Tq clock cycles1

3 Tq clock cycles1

4 Tq clock cycles

::::

15 Tq clock cycles

16 Tq clock cycles

76543210

WUPIF

CSCIF

RSTAT1

RSTAT0

TSTAT1

TSTAT0

OVRIF

RXF

Reset:

00000000

= Unimplemented

Figure 10-8. MSCAN Receiver Flag Register (CANRFLG)

Bit Time

Prescaler value

()

CANCLK

------------------------------------------------------

TimeSegment1

TimeSegment2

()

•

PC912XDP512F0CFVR bảng dữ liệu(PDF) 430 Page - Freescale Semiconductor, Inc

PC912XDP512F0CFVR bảng dữ liệu(HTML) 430 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL