PC912XDP512F0CFVR datasheet(416/1348 Pages) FREESCALE

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.21

416

Freescale Semiconductor

In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the

next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must

be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL

line so that the master can generate a STOP signal.

9.7.1.7

Arbitration Lost

If several masters try to engage the bus simultaneously, only one master wins and the others lose

arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the

hardware. Their data output to the SDA line is stopped, but SCL continues to be generated until the end of

the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this

transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission while the bus is being

engaged by another master, the hardware will inhibit the transmission; switch the MS/SL bit from 1 to 0

without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the

attempt to engage the bus is failed. When considering these cases, the slave service routine should test the

IBAL ﬁrst and the software should clear the IBAL bit if it is set.

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