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PC912XDP512F0CFVR bảng dữ liệu(PDF) 401 Page - Freescale Semiconductor, Inc

tên linh kiện PC912XDP512F0CFVR
Giải thích chi tiết về linh kiện  HCS12X Microcontrollers
PDF  1348 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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PC912XDP512F0CFVR bảng dữ liệu(HTML) 401 Page - Freescale Semiconductor, Inc

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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
401
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table 9-5. The equation used to generate the SDA Hold value from the IBFD bits is:
SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
Table 9-5. IIC Divider and Hold Values (Sheet 1 of 5)
IBC[7:0]
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)
MUL=1
00
20
7
6
11
01
22
7
7
12
02
24
8
8
13
03
26
8
9
14
04
28
9
10
15
05
30
9
11
16
06
34
10
13
18
07
40
10
16
21
08
28
7
10
15
09
32
7
12
17
0A
36
9
14
19
0B
40
9
16
21
0C
44
11
18
23
0D
48
11
20
25
0E
56
13
24
29
0F
68
13
30
35
10
48
9
18
25
11
56
9
22
29
12
64
13
26
33
13
72
13
30
37
14
80
17
34
41
15
88
17
38
45
16
104
21
46
53
17
128
21
58
65
18
80
9
38
41
19
96
9
46
49
1A
112
17
54
57
1B
128
17
62
65
1C
144
25
70
73
1D
160
25
78
81
1E
192
33
94
97
1F
240
33
118
121
20
160
17
78
81
21
192
17
94
97
22
224
33
110
113



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