PC912XDP512F0CFVR datasheet(215/1348 Pages) FREESCALE

215 / 1348 page

Chapter 6 XGATE (S12XGATEV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

215

6.8.3

Cycle Notation

Table 6-16 show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each letter

implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals are

not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible

every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit

operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle.

6.8.4

Thread Execution

When the RISC core is triggered by an interrupt request (see Figure 6-1) it ﬁrst executes a vector fetch

sequence which performs three bus accesses:

1. A V-cycle to fetch the initial content of the program counter.

2. A V-cycle to fetch the initial content of the data segment pointer (R1).

3. A P-cycle to load the initial opcode.

Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If

further interrupt requests are pending after a thread has been terminated, a new vector fetch will be

performed. Otherwise the RISC core will idle until a new interrupt request is received. A thread can not be

interrupted by an interrupt request.

6.8.5

Instruction Glossary

This section describes the XGATE instruction set in alphabetical order.

Table 6-16. Access Detail Notation

— Vector fetch: always an aligned word read, lasts for at least one RISC core cycle

— Program word fetch: always an aligned word read, lasts for at least one RISC core cycle

— 8 bit data read: lasts for at least one RISC core cycle

— 16 bit data read: lasts for at least one RISC core cycle

— 8 bit data write: lasts for at least one RISC core cycle

— 16 bit data write: lasts for at least one RISC core cycle

— Alignment cycle: no read or write, lasts for zero or one RISC core cycles

— Free cycle: no read or write, lasts for one RISC core cycles

Special Cases

PP/P

— Branch: PP if branch taken, P if not

PC912XDP512F0CFVR bảng dữ liệu(PDF) 215 Page - Freescale Semiconductor, Inc