56F8013 datasheet(8/126 Pages) FREESCALE

8 / 126 page

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

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Up to 26 General-Purpose I/O (GPIO) pins with 5V tolerance

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Integrated Power-On Reset and Low-Voltage Interrupt Module

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Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals

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Clock Sources:

— On-chip relaxation oscillator

— External clock source

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On-chip regulators for digital and analog circuitry to lower cost and reduce noise

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JTAG/EOnCE debug programming interface for real-time debugging

1.1.5

Energy Information

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Fabricated in high-density CMOS with 5V tolerance

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On-chip regulators for digital and analog circuitry to lower cost and reduce noise

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Wait and Stop modes available

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ADC smart power management

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Each peripheral can be individually disabled to save power

1.2 56F8013/56F8011 Description

The 56F8013/56F8011 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs).

It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller

with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56F8013/56F8011 is well-suited for many

applications. The 56F8013/56F8011 includes many peripherals that are especially useful for industrial

control, motion control, home appliances, general purpose inverters, smart sensors, fire and security

systems, switched mode power supply, power management, and medical monitoring applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient, compact

DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F8013/56F8011 supports program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. The 56F8013/56F8011 also offers up to 26

General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F8013 Digital Signal Controller includes 16KB of Program Flash and 4KB of Unified

Data/Program RAM. The 56F8011 Digital Signal Controller includes 12KB of Program Flash and 2KB

of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in

pages. Program Flash page erase size is 512 Bytes (256 Words).

A full set of programmable peripherals—PWM, ADCs, SCI, SPI, I2C, Quad Timer—supports various

applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals

can also be used as General Purpose Input/Outputs (GPIOs).

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