M41T62 datasheet(18/41 Pages) STMICROELECTRONICS

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Clock operation

M41T62/63/64/65

18/41

Doc ID 10397 Rev 14

3.1

RTC registers

The M41T6x user interface is comprised of 16 memory mapped registers which include

clock, calibration, alarm, watchdog, flags, and square wave control. The eight clock

counters are accessed indirectly via a set of buffer/transfer registers while the other eight

registers are directly accessed. Data in the clock and alarm registers is in BCD format.

Figure 20.

Buffer/transfer registers

Updates

During normal operation when the user is not accessing the device, the buffer/transfer

registers are kept updated with a copy of the RTC counters. At the start of an I2C read or

write cycle, the updating is halted and the present time is frozen in the buffer/transfer

registers.

Reads of the clock registers

By halting the updates at the start of an I2C access, the user is ensured that all the data

transferred out during a read sequence comes from the same instant in time.

32KHz

OSC

DIVIDE BY

32768

1 Hz

READ / WRITE

BUFFER

TRANSFER

REGISTERS

I2C

INTERFACE

CENTURIES

YEARS

MONTHS

DATE

DAY-OF-WEEK

HOURS

MINUTES

SECONDS

COUNTER

CLOCK COUNTERS ARE

ACCESSED INDIRECTLY

THRU BUFFER/TRANSFER

REGISTERS

FLAGS

NON-CLOCK

REGISTERS

CALIBRATION

WATCHDOG

NON-CLOCK REGISTERS

ARE DIRECTLY ACCESSED

DATA TRANSFERRED

OUT OF I2C INTERFACE

ON 8th FALLING EDGE

OF SCL (ON WRITES)

ON WRITES, DATA TRANSFERRED

FROM BUFFERS TO COUNTERS

WHEN ADDRESS POINTER

INCREMENTS TO 8 OR WHEN I2C

STOP CONDITION IS RECEIVED

AT START OF READ, UDATES FROM COUNTERS

ARE HALTED AND PRESENT TIME IS FROZEN

IN BUFFER/TRANSFER REGISTERS.

AM04890v1

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