ST7MC1XX datasheet(39/309 Pages) STMICROELECTRONICS

39 / 309 page

ST7MC1xx/ST7MC2xx

39/309

MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software

reading the CSR register. It indicates when set

that the main oscillator has reached the selected

elapsed time (TB1:0).

0: Timeout not reached

1: Timeout reached

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

MCC BEEP CONTROL REGISTER (MCCBCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = Reserved, must be kept cleared.

Bit 3 = ADSTS A/D Converter Sample Time

Stretch

This bit is set and cleared by software to enable or

disable the A/D Converter sample time stretch fea-

ture.

0: AD sample time stretch disabled (for standard

impedance analog inputs)

1 AD sample time stretch enabled (for high imped-

ance analog inputs)

Bit 2 = ADCIE A/D Converter Interrupt Enable

This bit is set and cleared by software to enable or

disable the A/D Converter interrupt.

0: AD Interrupt disabled

1 AD Interrupt enabled

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

The beep output signal is available in Active-halt

mode but has to be disabled to reduce the con-

sumption.

Table 5. Main Clock Controller Register Map and Reset Values

AD-

STS

ADC

BC1

BC0

BC1

BC0

Beep mode with fOSC2=8MHz

Off

~2-KHz

Output

Beep signal

~50% duty cycle

~1-KHz

~500-Hz

Address

(Hex.)

Label

765

432

0040h

SICSR, page0

Reset Value

PAGE

VDIE

VDF

LVDRF

CFIE

CSSD

WDGRF

0040h

SICSR, page1

Reset Value

PAGE

VCOEN

LOCK

PLLEN

CKSEL

002Ch

MCCSR

Reset Value

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

002Dh

MCCBCR

Reset Value

000

ADSTS

ADCIE

BC1

BC0

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