68HC705SP7 datasheet(153/230 Pages) FREESCALE

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Core Timer

COP Watchdog

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Core Timer

COPC — COP Clear

This write-only bit resets the COP watchdog. The COP watchdog is

active in the run, wait, and halt modes of operation if the COP is

enabled by setting the COPEN bit in the MOR. The STOP instruction

disables the COP watchdog by clearing the counter and turning off its

clock source.

In applications that depend on the COP watchdog, the STOP

instruction can be disabled by setting the SWAIT bit in the MOR. In

applications that have wait cycles longer than the COP timeout

period, the COP watchdog can be disabled by clearing the COPEN

bit. Table 10-2 summarizes recommended conditions for enabling

and disabling the COP watchdog.

NOTE:

If the voltage on the IRQ/VPP pin exceeds 1.5 × VDD, the COP watchdog

turns off and remains off until the IRQ/VPP pin voltage falls below

1.5

× V

DD.

Table 10-2. COP Watchdog Recommendations

Voltage on

IRQ/VPP Pin

SWAIT

(in MOR)1

Wait/Halt Time

Recommended COP

Watchdog Condition

Less than 1.5

× V

Less than COP Timeout Period

Enabled2

Less than 1.5

× V

Greater than COP Timeout Period

Disabled

Less than 1.5

× V

0X3

Disabled

More than 1.5

× V

Disabled

NOTES:

1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions.

2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.

3. X = don’t care.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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