TSA1002IF datasheet(13/20 Pages) STMICROELECTRONICS

13 / 20 page

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Product(s)

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TSA1002

13/20

Data Ready (DR)

The Data Ready output is an image of the clock

being synchronized on the output data (D0 to D9).

This is a very helpful signal that simplifies the

synchronization of the measurement equipment or

the controlling DSP.

As digital output, DR goes in high impedance state

when OEB is asserted to High level as described

in the timing diagram page 4.

REFERENCES AND COMMON MODE

CONNECTION

VREFM must be always connected externally.

Internal reference and common mode

In the default configuration, the ADC operates with

its own reference and common mode voltages

generated by its internal bandgap. VREFM pin is

connected externally to the Analog Ground while

VREFP (respectively INCM) is set to its internal

voltage of 1.03V (respectively 0.57V). It is

recommended to decouple the VREFP in order to

minimize low and high frequency noise (refer to

Figure 1)

Figure 1 : Internal reference and common mode

setting

External reference and common mode

Each of the voltages VREFM, VREFP and INCM

can be fixed externally to better fit to the

application needs (Refer to Table íOPERATING

CONDITIONSí p2 for min and max values).

The VREFP, VREFM voltages set the analog

dynamic at the input of the converter that has a full

scale amplitude of 2*(VREFP-VREFM).

In case of analog dynamic lower than 2Vpp, the

best linearity

and

distortion

performance

achieved while increasing the VREFM voltage

instead of lowering the VREFP one.

The INCM is the mid voltage of the analog input

signal.

It is possible to use an external reference voltage

device for specific applications requiring even

better

linearity,

accuracy

enhanced

temperature behavior.

Using

the

STMicroelectronics

TS821

TS4041-1.2 Vref leads to optimum performances

when configured as shown on Figure 2.

Figure 2 : External reference setting

At 15Msps sampling frequency, 1MHz input

frequency

and

-1dBFS

amplitude

signal,

performances can be improved up to 2dB on

SFDR and 0.3dB on SINAD. At 50Msps sampling

frequency, 1MHz input frequency and -1dBFS

amplitude signal, performances can be improved

up to 1dBc on SFDR and 0.6dB on SINAD.

This

can

very

helpful for

example

for

multichannel application to keep a good matching

among the sampling frequency range.

TSA1002

VIN

VINB

VREFM

1.03V

VREFP

330pF

4.7uF

10nF

INCM

330pF

4.7uF

10nF

0.57V

Ω

TSA1002

VIN

VINB

VREFM

VREFP

external

reference

VCCA

330pF

4.7uF

10nF

TS821

TS4041

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