STA015T datasheet(14/56 Pages) STMICROELECTRONICS

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Figure 14. Input from BITSTREAM, Output from GPSO

Figure 15. Input from ADC, Output from GPSO

5.0 I2C BUS SPECIFICATION

The STA015 supports the I2C protocol. This protocol defines any device that sends data on to the bus as

a transmitter and any device that reads the data as a receiver. The device that controls the data transfer

is known as the master and the others as the slave. The master always starts the transfer and provides

the serial clock for synchronisation. The STA015 is always a slave device in all its communications.

5.1 COMMUNICATION PROTOCOL

3.1.0 - Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock

is high are used to identify START or STOP condition.

5.1.1 Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is

stable in the high state. A START condition must precede any command for data transfer.

5.1.2 Stop condition

STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable

in the high state. A STOP condition terminates communications between STA015 and the bus master.

5.1.3 Acknowledge bit

An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or

slave, releases the SDA bus after sending 8 bit of data. During the 9th clock pulse the receiver pulls the

SDA bus low to acknowledge the receipt of 8 bits of data.

SDI

GPSO_REQ

GPSO_SCKR

GPSO_DATA

SCKR

LRCKT

SCKT

SDO

OCLK

DATA_REQ

MCU

DAC

STA015

BIT_EN

I2C

D99AU1122A

TQFP44

LFBGA64

GPSO_SCKR

GPSO_REQ

LRCK_ADC

SCK_ADC

SDI_ADC

GPSO_DATA

MCU

ADC

MASTER

DAC

STA015

D99AU1124A

OCLK

SDO

SCKT

LRCKT

TQFP44

LFBGA64

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