CAT521WI datasheet(7/13 Pages) ONSEMI

7 / 13 page

Not Recommended for New Design

CAT521

Doc. No. MD-2003 Rev. I

Characteristics subject to change without notice

No clock is necessary upon system power-up. The

CAT521 internal power-on reset circuitry loads data

from non-volatile memory to the DPP without using

the external clock.

As data transfers are edge triggered clean clock

transitions are necessary to avoid falsely clocking

data into the control register. Standard CMOS and

TTL logic families work well in this regard and it is

recommended that any mechanical switches used for

breadboarding or device evaluation purposes be

debounced by a flip-flop or other suitable debouncing

circuit.

VREF

VREF, the voltage applied between pins VREFH & VREFL,

sets the DPP’s Zero to Full Scale output range where

VREFL = Zero and VREFH = Full Scale. VREF can span

the full power supply range or just a fraction of it. In

typical applications VREFH & VREFL are connected

across the power supply rails. When using less than

the full supply voltage be mindfull of the limits placed

on VREFH and VREFL as specified in the References

section of DC Electrical Characteristics.

READY/BUSY

¯¯¯¯¯

When saving data to non-volatile memory, the

Ready/Busy ouput (RDY/BSY

¯¯¯¯) signals the start and

duration of the erase/write cycle. Upon receiving a

command to store data (PROG goes high) RDY/BSY

¯¯¯¯

goes low and remains low until the programming cycle is

complete. During this time the CAT521 will ignore any

data appearing at DI and no data will be output on DO.

RDY/BSY

¯¯¯¯ is internally ANDed with a low voltage

detector circuit monitoring VDD. If VDD is below the

minimum value required for EEPROM programming,

RDY/BSY

¯¯¯¯ will remain high following the program

command indicating a failure to record the desired

data in non-volatile memory.

DATA OUTPUT

Data is output serially by the CAT521, LSB first, via

the Data Out (DO) pin following the reception of a

start bit and two address bits by the Data Input (DI).

DO becomes active whenever CS goes high and

resumes its high impedance Tri-State mode when CS

returns low. Tri-Stating the DO pin allows several

521s to share a single serial data line and simplifies

interfacing multiple 521s to a microprocessor.

WRITING TO MEMORY

Programming the CAT521’s non-volatile memory is

accomplished through the control signals: Chip Select

(CS) and Program (PROG). With CS high, a start bit

followed by a two bit DPP address and eight data bits

are clocked into the DPP wiper control register via the

DI pin. Data enters on the clock’s rising edge. The

DPP output changes to its new setting on the clock

cycle following D7, the last data bit.

Programming is accomplished by bringing PROG high

sometime after the start bit and at least 150ns prior to

the rising edge of the clock cycle immediately

following the D7 bit. Two clock cycles after the D7 bit

the DPP wiper control register will be ready to receive

the next set of address and data bits. The clock must

be kept running throughout the programming cycle.

Internal control circuitry takes care of generating and

ramping up the programming voltage for data transfer

to the non-volatile memory cells. The CAT521 non-

volatile memory cells will endure over 1,000,000 write

cycles and will retain data for a minimum of 100 years

without being refreshed.

Figure 1. Writing to Memory

NEW DPP DATA

CURRENT DPP DATA

CURRENT

DPP VALUE

NON-VOL ATILE

DPP

OUTPUT

PROG

NEW

DPP VALUE

VOLATILE

NEW

DPP VALUE

NON-VOL ATILE

N+1 N+2

RDY/BSY

CAT521WI bảng dữ liệu(PDF) 7 Page - ON Semiconductor

CAT521WI bảng dữ liệu(HTML) 7 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

bảng dữ liệu tải về

Link URL