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CAT521 bảng dữ liệu(PDF) 4 Page - ON Semiconductor

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Giải thích chi tiết về linh kiện  Configured Digitally Programmable Potentiometer (DPP??: Programmable Voltage Applications
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CAT521
Not Recommended for New Design
Doc. No. MD-2003 Rev. I
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Potentiometer Resistance
See note 3
24
kΩ
RPOT to RPOT Match
—
±0.5
±1
%
Pot Resistance Tolerance
±20
%
Voltage on VREFH pin
2.7
VDD
V
Voltage on VREFL pin
0
VDD - 2.7
V
RPOT
Resolution
0.4
%
INL
Integral Linearity Error
0.5
1
LSB
DNL
Differential Linearity Error
0.25
0.5
LSB
ROUT
Buffer Output Resistance
10
Ω
IOUT
Buffer Output Current
3
mA
TCRPOT
TC of Pot Resistance
300
ppm/ºC
CH/CL
Potentiometer Capacitances
8/8
pF
AC ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Digital
tCSMIN
Minimum CS Low Time
150
—
—
ns
tCSS
CS Setup Time
100
—
—
ns
tCSH
CS Hold Time
0
—
—
ns
tDIS
DI Setup Time
50
—
—
ns
tDIH
DI Hold Time
50
—
—
ns
tDO1
Output Delay to 1
—
—
150
ns
tDO0
Output Delay to 0
CL = 100pF
(1)
—
—
150
ns
tHZ
Output Delay to High-Z
—
400
—
ns
tLZ
Output Delay to Low-Z
—
400
—
ns
tBUSY
Erase/Write Cycle Time
—
4
5
ms
tPS
PROG Setup Time
150
—
—
ns
tPROG
Minimum Pulse Width
700
—
—
ns
tCLKH
Minimum CLK High Time
500
—
—
ns
tCLKL
Minimum CLK Low Time
300
—
—
ns
fC
Clock Frequency
DC
—
1
MHz
Analog
tDS
DPP Settling Time to 1 LSB
CLOAD = 10pF, VDD = +5V
—
3
10
µs
CLOAD = 10pF, VDD = +3V
—
6
10
µs
Notes:
(1) All timing measurements are defined at the point of signal crossing VDD / 2.
(2) These parameters are periodically sampled and are not 100% tested.
(3) The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and VREFL of 6kΩ
+20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value.



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