DSP56300FM datasheet(49/104 Pages) FREESCALE

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AC Electrical Characteristics

DSP56L307 Technical Data, Rev. 6

Freescale Semiconductor

2-29

2.4.5.5 Asynchronous Bus Arbitration Timings

The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These

synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this

delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is deasserted. This is the

reason for timing 250.

Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other

DSP56300 components that are potential masters on the same bus. If BG input is asserted before that time, and BG

is asserted and BB is deasserted, another DSP56300 component may assume mastership at the same time.

Therefore, some non-overlap period between one BG input active to another BG input active is required. Timing 251

ensures that overlaps are avoided.

Table 2-16.

Asynchronous Bus Timings

No.

Characteristics

Expression

100 MHz

160 MHz

Unit

Min

Max

Min

Max

250

BB assertion window from BG input deassertion.

2.5

× Tc + 5

—

20.6

251

Delay from BB assertion to BG assertion

× Tc + 5

—

17.5

—

Notes:

Bit 13 in the Operating Mode Register must be set to enable Asynchronous Arbitration mode.

At 160 MHz, Asynchronous Arbitration mode is recommended.

To guarantee timings 250 and 251, it is recommended that you assert non-overlapping BG inputs to different DSP56300

devices (on the same bus), as shown in Figure 2-21, where BG1 is the BG signal for one DSP56300 device while BG2 is the

BG signal for a second DSP56300 device.

Figure 2-21.

Asynchronous Bus Arbitration Timing

BG1

251

BG2

250

250+251

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