ADS1258IPHPREP datasheet(45/57 Pages) TI

45 / 57 page

ADS1258-EP

www.ti.com

SBAS445C – MARCH 2009 – REVISED DECEMBER 2009

Clock Source: The ADS1258 requires a clock

for more details. The SPI interface can be

signal for operation. The clock can originate from

operated in a minimum configuration without the

either the crystal oscillator or from an external

use of CS (tie CS low; see the Serial Interface

clock source. The internal oscillator uses a PLL

and Communication Protocol sections).

circuit and an external 32.768-kHz crystal to

GPIO:

The

ADS1258

has

eight,

user-

generate a 15.7-MHz master clock. The PLL

programmable digital I/O pins. These pins are

requires a 22-nF capacitor from the PLLCAP pin

controlled

settings.

The

to AVSS. The crystal and load capacitors should

setting is default to inputs. If these pins are not

be placed close to the pins as possible and kept

used, tie them high or low (do not float input pins)

away from other traces with AC components. A

or configure them as outputs.

buffered output of the 15.7-MHz clock can be

k. QFN Package: See Application Report SLUA271,

used to drive other converters or controllers. An

QFN/SON PCB Attachment for PCB layout

external clock source can be used up to 16 MHz.

recommendations,

available

for

download

For best performance, the clock of the SPI

www.ti.com. The exposed thermal pad of the

interface controller and the converter itself should

ADS1258 should be connected electrically to

be on the same domain. This configuration

AVSS.

requires that the ratio of the SCLK to device clock

must be limited to 1,1/2,1/4, 1/8, etc.

CONFIGURATION GUIDE

g. Digital Inputs: It is recommended to source

Configuration of the ADS1258 involves setting the

terminate the digital inputs and outputs of the

configuration registers via the SPI interface. After the

device with a 50-

Ω (typical) series resistor. The

device is configured for operation, channel data is

resistors should be placed close to the driving

read from the device through the same SPI interface.

end of the source (output pins, oscillator, logic

The

following

suggested

procedure

for

gates, DSP, etc). This placement helps to reduce

configuring the device:

the ringing and overshoot on the digital lines.

1. Reset the SPI Interface: Before using the SPI

h. Hardware Pins: START, DRDY, RESET, and

interface, it may be necessary to recover the SPI

PWDN. These pins allow direct pin control of the

interface. To reset the interface, set CS high or

ADS1258. The equivalent of the START and

disable SCLK for 4096 (256) fCLK cycles.

DRDY pins is provided via commands through

the SPI interface; these pins may be left unused.

2. Stop the Converter: Set the START pin low to

The device also has a RESET command. The

stop the converter. Although not necessary for

PWDN pin places the ADC into very low-power

configuration, this command stops the channel

state

where

the

device

inactive.

scanning sequence which then points to the first

channel after configuration.

SPI

Interface:

The

ADS1258

has

SPI-compatible interface. This interface consists

3. Reset the Converter: The reset pin can be

of four signal lines: SCLK, DIN, DOUT, and CS.

pulsed low or a Reset command can be sent.

When CS is high, the DIN input is ignored and

Although not necessary for configuration, reset

the DOUT output tri-states. See Chip Select (CS )

re-initializes the device into a known state.

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Product Folder Link(s): ADS1258-EP

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