TUSB9260

www.ti.com

SLLS962A – DECEMBER 2009 – REVISED JULY 2010

4.4

Power Up and Reset Sequence

The TUSB9260 does not have specific power sequencing requirements with respect to the core power

(VDD), I/O power (VDD33), or analog power (VDDA11, VDDA33, VDDA18, and VDDR18). The core

power (VDD) or IO power (VDD33) may be powered up for an indefinite period of time while others are not

powered up if all of these constraints are met:

•

All maximum ratings and recommended operating conditions are observed.

•

All warnings about exposure to maximum rated and recommended conditions are observed,

par-ticularly junction temperature. These apply to power transitions as well as normal operation.

•

Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of

the device.

•

Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered

down when it is below that range, either stable or in transition.

A minimum reset duration of 1 ms is required. This is defined as the time when the power supplies are in

the recommended operating range to the de-assertion of GRSTz.

Copyright © 2009–2010, Texas Instruments Incorporated

OPERATION

11

Submit Documentation Feedback

Product Folder Link(s): TUSB9260