PIC18F23K22-ESLASHML datasheet(67/492 Pages) MICROCHIP

67 / 492 page

 2010 Microchip Technology Inc.

Preliminary

DS41412B-page 67

PIC18(L)F2X/4XK22

4.6

Reset State of Registers

Some registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. All other registers are forced to a “Reset state”

depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal

operation. Status bits from the RCON register, RI, TO,

PD, POR and BOR, are set or cleared differently in

different Reset situations, as indicated in Table 4-3.

These bits are used by software to determine the

nature of the Reset.

Table 5-2 describes the Reset states for all of the

Special Function Registers. The table identifies

differences between Power-On Reset (POR)/Brown-

Out Reset (BOR) and all other Resets, (i.e., Master

Clear, WDT Resets, STKFUL, STKUNF, etc.).

Additionally, the table identifies register bits that are

changed when the device receives a wake-up from

WDT or other interrupts.

TABLE 4-3:

STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION

FOR RCON REGISTER

Condition

Program

Counter

RCON Register

STKPTR Register

SBOREN

POR BOR STKFUL

STKUNF

Power-on Reset

0000h

111

RESET Instruction

0000h

u(2)

0uu

Brown-out Reset

0000h

u(2)

111

MCLR during Power-Managed

Run Modes

0000h

u(2)

u1u

MCLR during Power-Managed

Idle Modes and Sleep Mode

0000h

u(2)

u10

WDT Time-out during Full Power

or Power-Managed Run Mode

0000h

u(2)

u0u

MCLR during Full Power

Execution

0000h

u(2)

uuu

Stack Full Reset (STVREN = 1)

0000h

u(2)

uuu

Stack Underflow Reset

(STVREN = 1)

0000h

u(2)

uuu

Stack Underflow Error (not an

actual Reset, STVREN = 0)

0000h

u(2)

uuu

WDT Time-out during

Power-Managed Idle or Sleep

Modes

PC + 2

u(2)

u00

Interrupt Exit from

Power-Managed Modes

PC + 2(1)

u(2)

uu0

Legend: u = unchanged

Note 1:

When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (008h or 0018h).

Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled

(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.

TABLE 4-4:

REGISTERS ASSOCIATED WITH RESETS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

RCON

IPEN

SBOREN

—RI

POR

BOR

STKPTR

STKFUL

STKUNF

—

STKPTR<4:0>

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.

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