PIC18F4580-ESLASHML datasheet(64/490 Pages) MICROCHIP

64 / 490 page

PIC18F2480/2580/4480/4580

DS39637D-page 64

B2D1(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B2D0(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B2DLC(6)

2480 2580 4480 4580

-xxx xxxx

-uuu uuuu

B2EIDL(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B2EIDH(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B2SIDL(6)

2480 2580 4480 4580

xxxx x-xx

uuuu u-uu

B2SIDH(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B2CON(6)

2480 2580 4480 4580

0000 0000

uuuu uuuu

B1D7(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1D6(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1D5(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1D4(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1D3(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1D2(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1D1(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1D0(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1DLC(6)

2480 2580 4480 4580

-xxx xxxx

-uuu uuuu

B1EIDL(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1EIDH(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1SIDL(6)

2480 2580 4480 4580

xxxx x-xx

uuuu u-uu

B1SIDH(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B1CON(6)

2480 2580 4480 4580

0000 0000

uuuu uuuu

B0D7(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B0D6(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B0D5(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B0D4(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B0D3(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B0D2(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B0D1(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B0D0(6)

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

B0DLC(6)

2480 2580 4480 4580

-xxx xxxx

-uuu uuuu

TABLE 5-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 5-3 for Reset value for specific condition.

Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F4580-E/ML bảng dữ liệu(PDF) 64 Page - Microchip Technology

PIC18F4580-E/ML bảng dữ liệu(HTML) 64 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL