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PIC18F4580-E/ML bảng dữ liệu(PDF) 217 Page - Microchip Technology

tên linh kiện PIC18F4580-E/ML
Giải thích chi tiết về linh kiện  28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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© 2009 Microchip Technology Inc.
DS39637D-page 217
PIC18F2480/2580/4480/4580
18.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 18-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 18-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 18-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 18-3:
I2C™ CLOCK RATE W/BRG
FCY
FCY*2
BRG Value
FSCL
(2 Rollovers of BRG)
10 MHz
20 MHz
19h
400 kHz
10 MHz
20 MHz
20h
312.5 kHz
10 MHz
20 MHz
64h
100 kHz
4 MHz
8 MHz
0Ah
400 kHz
4 MHz
8 MHz
0Dh
308 kHz
4 MHz
8 MHz
28h
100 kHz
1 MHz
2 MHz
03h
333 kHz
1 MHz
2 MHz
0Ah
100 kHz
SSPM<3:0>
BRG Down Counter
CLKO
FOSC/4
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control
Reload



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