PIC16F1934-ESLASHML datasheet(129/508 Pages) MICROCHIP

129 / 508 page

 2009 Microchip Technology Inc.

Preliminary

DS41364D-page 129

PIC16F193X/LF193X

12.0

I/O PORTS

Depending on the device selected and peripherals

enabled, there are up to five ports available. In general,

when a peripheral is enabled, that pin may not be used

as a general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRISx registers (data direction register)

• PORTx registers (reads the levels on the pins of

the device)

• LATx registers (output latch)

The Data Latch (LATx registers) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

A write operation to the LATx register has the same

affect as a write to the corresponding PORTx register.

A read of the LATx register reads of the values held in

the I/O PORT latches, while a read of the PORTx

Ports with analog functions also have an ANSELx

power. A simplified model of a generic I/O port, without

the interfaces to other peripherals, is shown in

Figure 12-1.

FIGURE 12-1:

GENERIC I/O PORT

OPERATION

12.1

Alternate Pin Function

The Alternate Pin Function Control (APFCON) register

is used to steer specific peripheral input and output

functions between different pins. The APFCON register

is shown in Register 12-1. For this device family, the

following functions can be moved between different

pins.

•SS (Slave Select)

• P2B output

• CCP2/P2A output

• CCP3/P3A output

• Timer1 Gate

• SR Latch SRNQ output

• Comparator C2 output

These bits have no effect on the values of any TRIS

correct pin. The unselected pin will be unaffected.

Write LATx

Data Register

I/O pin

Read PORTx

Write PORTx

TRISx

Read LATx

Data Bus

To peripherals

ANSELx

VDD

VSS

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