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PIC16F1934-E/ML bảng dữ liệu(PDF) 121 Page - Microchip Technology |
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PIC16F1934-E/ML bảng dữ liệu(HTML) 121 Page - Microchip Technology |
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121 / 508 page ![]() 2009 Microchip Technology Inc. Preliminary DS41364D-page 121 PIC16F193X/LF193X After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 8 WRITE LATCHES 14 14 14 14 Program Memory Buffer Register EEADRL<2:0> = 000 Buffer Register EEADRL<2:0> = 001 Buffer Register EEADRL<2:0> = 010 Buffer Register EEADRL<2:0> = 111 EEDATA EEDATH 75 07 0 6 8 First word of block to be written Last word of block to be written |
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