PIC12F519-ESLASHMS datasheet(16/96 Pages) MICROCHIP

16 / 96 page

PIC12F519

DS41319B-page 14

4.2

Data Memory (SRAM and FSRs)

Data memory is composed of registers or bytes of

SRAM. Therefore, data memory for a device is speci-

fied by its register file. The register file is divided into

two functional groups: Special Function Registers

(SFR) and General Purpose Registers (GPR).

The Special Function Registers include the TMR0

EEADR registers provide for interface with the Flash

data memory.

The PIC12F519 register file is composed of 10 Special

Function Registers and 41 General Purpose Registers.

4.2.1

GENERAL PURPOSE REGISTER

FILE

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 4.8 “Indirect Data Addressing:

INDF and FSR Registers”

FIGURE 4-2:

4.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the

operation of the device (Table 4-1).

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

0Fh

10h

Bank 0

Bank 1

3Fh

30h

20h

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

08h

Note 1:

Not a physical register.

FSR<5>

2Fh

09h

0Ah

INDF(1)

EECON

PCL

STATUS

FSR

EEDATA

EEADR

Address map

back to

addresses

in Bank 0

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