PIC18F14K22-ESLASHML datasheet(79/388 Pages) MICROCHIP

79 / 388 page

 2010 Microchip Technology Inc.

Preliminary

DS41365D-page 79

PIC18F1XK22/LF1XK22

8.0

I/O PORTS

There are up to three ports available. Some pins of the

I/O ports are multiplexed with an alternate function from

the peripheral features on the device. In general, when

a peripheral is enabled, that pin may not be used as a

general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

• PORT register (reads the levels on the pins of the

device)

• LAT register (output latch)

The PORTA Data Latch (LATA register) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

A simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 8-1.

FIGURE 8-1:

GENERIC I/O PORT

OPERATION

8.1

PORTA, TRISA and LATA

Registers

PORTA is 5 bits wide. PORTA<5:4,2:0> bits are

bidirectional ports and PORTA is an input-only port.

The corresponding data direction register is TRISA.

Setting a TRISA bit (= 1) will make the corresponding

PORTA pin an input (i.e., disable the output driver).

Clearing a TRISA bit (= 0) will make the corresponding

PORTA pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins, whereas writing to it, will write to the PORT latch.

The PORTA Data Latch (LATA) register is also memory

mapped. Read-modify-write operations on the LATA

PORTA.

All of the PORTA pins are individually configurable as

interrupt-on-change pins. Control bits in the IOCA

interrupt function for each pin.

When set, the RABIE bit of the INTCON register

enables interrupts on all pins which also have their

corresponding IOCA bit set. When clear, the RABIE

bit disables all interrupt-on-changes.

Only pins configured as inputs can cause this interrupt

to occur (i.e., any pin configured as an output is

excluded from the interrupt-on-change comparison).

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTA. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTA Change Interrupt flag

bit (RABIF) in the INTCON register.

Data

Bus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

Input

Buffer

I/O pin(1)

RD LAT

or Port

Note 1:

I/O pins have diode protection to VDD and VSS.

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