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 2010 Microchip Technology Inc.
Preliminary
DS22067H-page 11
11AAXXX/11LCXXX
4.2
Current Address Read (CRRD)
Instruction
The internal address counter featured on the 11XX
maintains the address of the last memory array loca-
tion accessed. The
CRRD instruction allows the mas-
ter to read data back beginning from this current
location. Consequently, no word address is provided
upon issuing this command.
Note that, except for the initial word address, the
READ and CRRD instructions are identical, including
the ability to continue requesting data through the use
of MAKs in order to sequentially read from the array.
As with the
READ instruction, the CRRD instruction is
terminated by transmitting a NoMAK.
Table 4-2 lists the events upon which the internal
address counter is modified.
TABLE 4-2:
INTERNAL ADDRESS
COUNTER
FIGURE 4-2:
CRRD COMMAND SEQUENCE
Command
Event
Action
—
Power-on Reset Counter is undefined
READ or
WRITE
MAK edge fol-
lowing each
Address byte
Counter is updated
with newly received
value
READ,
WRITE, or
CRRD
MAK/NoMAK
edge following
each data byte
Counter is incre-
mented by 1
Note: If, following each data byte in a
READ,
WRITE, or CRRD instruction, neither a
MAK nor a NoMAK edge is received
(i.e., if a standby pulse occurs instead),
the internal address counter will not be
incremented.
Note: During a Write command, once the last
data byte for a page has been loaded,
the internal Address Pointer will rollover
to the beginning of the selected page.
76 5 4
Data Byte 1
32 1 0
76 5 4
Data Byte 2
32 1 0
76 5 4
Data Byte n
32 1 0
SCIO
11
0
1
0
1
00
Start Header
SCIO
Device Address
00(1)
0
0
1
0
10
Command
10
0
0
0
0
01
Standby Pulse
SCIO
Note 1: For the 11XXXX1, this bit must be a ‘1’.



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