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HT86AR72 bảng dữ liệu(PDF) 47 Page - Holtek Semiconductor Inc |
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HT86AR72 bảng dữ liệu(HTML) 47 Page - Holtek Semiconductor Inc |
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47 / 68 page ![]() HT86Axx/HT86ARxx Rev. 1.00 47 March 19, 2010 SPI Serial Interface The device includes a single SPI Serial Interfaces. The SPI interface is a full duplex serial data link, originally designed by Motorola, which allows multiple devices connected to the same SPI bus to communicate with each other. The devices communicate using a mas- ter/slave technique where only the single master device can initiate a data transfer. A simple four line signal bus is used for all communication. The four SPI lines are shared with I/O pins PD0~PD3, the function of which is chosen using a configuration option. SPI Interface Communication Four lines are used for SPI communication known as SDI - Serial Data Input, SDO - Serial Data Output, SCK - Serial Clock and SCS - Slave Select. Note that the con- dition of the Slave Select line is conditioned by the CSEN bit in the SBCR control register. If the CSEN bit is high then the SCS line is active while if the bit is low then the SCS line will be in a floating condition. The following timing diagram depicts the basic timing protocol of the SPI bus. D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 S B D R ( R e c e i v e d D a t a R e g i s t e r ) M U X S D O B u f f e r M U X M L S D a t a B u s M U X M a s t e r o r S l a v e S D I S D O I n t e r n a l B a u d R a t e C l o c k S C K C l o c k P o l a r i t y C 2 C 1 C 0 S B E N I n t e r n a l B u s y F l a g S B E N W r i t e S B D R W C O L F l a g T R F a n d , s t a r t S B E N E N A N D W r i t e S B D R W r i t e S B D R E n a b l e / D i s a b l e S C S E N M a s t e r o r S l a v e C S E N S B E N a n d , s t a r t a n d , s t a r t SPI Block Diagram S B C R D E F A U L T S B D R D E F A U L T N o t e : " U " m e a n s u n c h a n g e d . C K S M 1 M 0 S B E N M L S C S E N W C O L T R F D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 1 1 0 0 0 0 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 U U U U U U U U S B C R : S E R I A L B U S C O N T R O L R E G I S T E R S B D R : S E R I A L B U S D A T A R E G I S T E R D 7 / D 0 D 6 / D 1 D 5 / D 2 D 4 / D 3 D 3 / D 4 D 2 / D 5 D 1 / D 6 D 0 / D 7 S D O D 7 / D 0 D 6 / D 1 D 5 / D 2 D 4 / D 3 D 3 / D 4 D 2 / D 5 D 1 / D 6 D 0 / D 7 S D I S C K S C S |
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