Rev 1.00

March 22, 2010

17

HT45B0K

SPI to USB Bridge

FIFO0~FIFO5 Registers

The FIFO0~FIFO5 Registers are used for data transactions between the USB device and the USB

host. The MCU reads data from or writes data to the FIFOs via the SPI interface to complete

data interchange. For “Interrupt transfer” it is supported by FIFO0~FIFO2 and FIFO4, while it is

supported by FIFO3 and FIFO5 for “Bulk transfer”.

FIFO0~FIFO5 Registers

Label

Type

POR

MISC Setting Flow and Status

FIFO0

R/W

xxxx xxxx

Data pipe for endpoint 0, depth = 8 bytes

FIFO1

R/W

xxxx xxxx

Data pipe for endpoint 1, depth = 8 bytes

FIFO2

R/W

xxxx xxxx

Data pipe for endpoint 2, depth = 8 bytes

FIFO3

R/W

xxxx xxxx

Data pipe for endpoint 3, depth = 64 bytes

FIFO4

R/W

xxxx xxxx

Data pipe for endpoint 4, depth = 8 bytes

FIFO5

R/W

xxxx xxxx

Data pipe for endpoint 5, depth = 64 bytes

“x” means unknown.