PIMC31_1

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 01 — 24 March 2009

2 of 13

NXP Semiconductors

PIMC31

500 mA, 50 V NPN/PNP double RET; R1 = 1 k

Ω, R2 = 10 kΩ

2.

Pinning information

3.

Ordering information

4.

Marking

5.

Limiting values

Table 2.

Pinning

Pin

Description

Simplified outline

Graphic symbol

1

GND (emitter) TR1

2

input (base) TR1

3

output (collector) TR2

4

GND (emitter) TR2

5

input (base) TR2

6

output (collector) TR1

13

2

4

5

6

65

4

1

23

R2

TR1

TR2

R1

R2

R1

006aaa143

Table 3.

Ordering information

Type number

Package

Name

Description

Version

PIMC31

SC-74

plastic surface-mounted package (TSOP6); 6 leads

SOT457

Table 4.

Marking codes

Type number

Marking code

PIMC31

ZH

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

Per transistor; for the PNP transistor with negative polarity

collector-base voltage

open emitter

-

50

V

collector-emitter voltage

open base

-

50

V

emitter-base voltage

open collector

-

5

V

input voltage TR1

positive

-

+10

V

negative

-

−5V

input voltage TR2

positive

-

+5

V

negative

-

−10

V