PCF8578HSLASH1 datasheet(30/46 Pages) NXP

30 / 46 page

PCF8578_6

Product data sheet

Rev. 06 — 5 May 2009

30 of 46

NXP Semiconductors

PCF8578

LCD row/column driver for dot matrix graphic displays

11. Dynamic characteristics

Table 18.

Dynamic characteristics

All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD.VDD = 2.5 V to 6 V; VSS =0V;

VLCD =VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fclk

clock frequency

at multiplex rate 1:8, 1:16

and 1:32;

Rext(OSC) = 330 kΩ;

VDD =6V

1.2

2.1

3.3

kHz

at multiplex rate 1:24;

Rext(OSC) = 330 kΩ;

VDD =6V

0.9

1.6

2.5

kHz

tPD(SYNC_N) SYNC propagation delay

500

tPD(drv)

driver propagation delay

VDD − VLCD =9V;

with test load of 45 pF

100

µs

I2C-bus

fSCL

SCL clock frequency

100

kHz

tw(spike)

spike pulse width

100

tBUF

bus free time between a STOP

and START condition

4.7

µs

tSU;STA

set-up time for a repeated START

condition

4.7

µs

tHD;STA

hold time (repeated) START

condition

4.0

µs

tLOW

LOW period of the SCL clock

4.7

µs

tHIGH

HIGH period of the SCL clock

4.0

µs

rise time of both SDA and SCL

signals

--1

µs

fall time of both SDA and SCL

signals

0.3

µs

tSU;DAT

data set-up time

250

tHD;DAT

data hold time

tSU;STO

set-up time for STOP condition

4.0

µs

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