PCF8562TTSLASHS400SLASH2 datasheet(24/36 Pages) NXP

24 / 36 page

PCF8562_4

Product data sheet

Rev. 04 — 18 March 2009

24 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

[1]

The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

[1]

Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[2]

Alternating RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.18 Display controller

The display controller executes the commands identiﬁed by the command decoder. It

contains the device’s status registers and coordinates their effects. The display controller

is also responsible for loading display data into the display RAM in the correct ﬁlling order.

7.19 Multiple chip operation

For large display conﬁgurations or for more segments (> 128 elements) to drive please

refer to the PCF8576D device.

The contact resistance between the SYNC input/output on each cascaded device must be

controlled. If the resistance is too high, the device will not be able to synchronize properly;

this is particularly applicable to chip-on-glass applications. The maximum SYNC contact

resistance allowed for the number of devices in cascade is given in Table 14.

Table 12.

Bank-select command bits description

Bit

Symbol

Value

Description

Static

1:2 multiplex[1]

0, 1

see Table 8

6 to 2

11110

ﬁxed value

input bank selection; storage of arriving display data

RAM bit 0

RAM bits 0 and 1

RAM bit 2

RAM bits 2 and 3

output bank selection; retrieval of LCD display data

RAM bit 0

RAM bits 0 and 1

RAM bit 2

RAM bits 2 and 3

Table 13.

Blink-select command bits description

Bit

Symbol

Value

Description

0, 1

see Table 8

6 to 3

1110

ﬁxed value

blink mode selection

normal blinking[1]

alternate RAM bank blinking[2]

1 to 0

BF[1:0]

blink frequency selection

off

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