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P89LPC9402 bảng dữ liệu(PDF) 7 Page - NXP Semiconductors |
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P89LPC9402 bảng dữ liệu(HTML) 7 Page - NXP Semiconductors |
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7 / 60 page ![]() P89LPC9402_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 22 April 2009 7 of 60 NXP Semiconductors P89LPC9402 8-bit microcontroller with accelerated two-clock 80C51 core 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 5. Pin configuration P89LPC9402 P0.5/CMPREF/KBI5 S17 P0.4/CIN1A/KBI4 S16 P0.3/CIN1B/KBI3 S15 P0.2/CIN2A/KBI2 S14 P0.1/CIN2B/KBI1 S13 P2.0 S12 P2.1 S11 P0.0/CMP2/KBI0 S10 P1.7 S9 P1.6 S8 P1.5/RST S7 VSS S6 P3.1/XTAL1 S5 P3.0/XTAL2/CLKOUT S4 P1.4/INT1 S3 P1.3/INT0/SDA S2 002aae473 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Table 3. Pin description Symbol Pin Type Description P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.14.1 “Port configurations” and Table 12 “Static electrical characteristics” for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt trigger inputs. Port 0 also provides various special functions as described below: P0.0/CMP2/ KBI0 8 I/O P0.0 — Port 0 bit 0. O CMP2 — Comparator 2 output I KBI0 — Keyboard input 0. |
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