IMX51A datasheet(76/172 Pages) FREESCALE

76 / 172 page

i.MX51A Automotive and Infotainment Applications Processors, Rev. 2

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

4.7.4.3

MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 71 lists MII asynchronous inputs signal timing information. Figure 44 shows MII asynchronous

input timings listed in Table 71.

Figure 44. MII Async Inputs Timing Diagram

4.7.4.4

MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 72 lists MII serial management channel timings. Figure 45 shows MII serial management channel

timings listed in Table 72. The MDC frequency should be equal to or less than 2.5 MHz to be compliant

with the IEEE 802.3 MII specification. However the FEC can function correctly with a maximum MDC

frequency of 15 MHz.

Table 71. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

M91

1 FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

FEC_CRS to FEC_COL minimum pulse width

1.5

—

FEC_TX_CLK period

Table 72. MII Transmit Signal Timing

Characteristic

Min

Max

Unit

M10

FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)

—

M11

FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)

—

M12

FEC_MDIO (input) to FEC_MDC rising edge setup

—

M13

FEC_MDIO (input) to FEC_MDC rising edge hold

—

M14

FEC_MDC pulse width high

40% 60% FEC_MDC period

M15

FEC_MDC pulse width low

40% 60% FEC_MDC period

FEC_CRS, FEC_COL

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