P89LPC913FDH datasheet(31/66 Pages) NXP

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P89LPC912_913_914_5

Product data sheet

Rev. 05 — 28 September 2007

31 of 66

NXP Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

8.7 CCLK wake-up delay

The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it

stabilizes depending on the clock source used. If the clock source is any of the three

crystal selections (P89LPC912, P89LPC913) the delay is 992 OSCCLK cycles plus 60

µs

to 100

µs. If the clock source is either the internal RC oscillator, watchdog oscillator, or

external clock, the delay is 224 OSCCLK cycles plus 60

µsto100 µs.

8.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

8.9 Low power select

The P89LPC912 and P89LPC913 are designed to run at 18 MHz (CCLK) maximum.

However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1

to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest

performance access. This bit can then be set in software if CCLK is running at 8 MHz or

slower.

8.10 Memory organization

The various P89LPC912/913/914 memory spaces are as follows:

Fig 12. Block diagram of oscillator control (P89LPC914)

CPU

WDT

SPI

DIVM

÷2

oscclk

cclk

pclk

rcclk

002aaa483

(7.3728 MHz

± 1 %)

(400 kHz

+ 30 % − 20 %)

OSCILLATOR

WATCHDOG

OSCILLATOR

TIMER 0/

TIMER 1

BAUDRATE

GENERATOR

UART

RTC

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