M23LR64-R-MB6TSLASH2 datasheet(49/126 Pages) STMICROELECTRONICS

tên linh kiện	M23LR64-R-MB6T/2

Giải thích chi tiết về linh kiện	64 Kbit EEPROM with password protection & dual interface: 400kHz I²C serial bus & ISO 18000-3 mode 1 RF protocol at 13.56MHz

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49 / 126 page

M24LR64-R

Bit representation and coding

Doc ID 15170 Rev 9

49/126

11.2

Bit coding using two subcarriers

11.3

High data rate

A logic 0 starts with 8 pulses at 423.75 kHz (fC/32) followed by 9 pulses at 484.28 kHz

(fC/28) as shown in Figure 31. For the Fast commands, the x2 mode is not available.

Figure 31.

Logic 0, high data rate

A logic 1 starts with 9 pulses at 484.28 kHz (fC/28) followed by 8 pulses at 423.75 kHz

(fC/32) as shown in Figure 32. For the Fast commands, the x2 mode is not available.

Figure 32.

Logic 1, high data rate

11.4

Low data rate

A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by 36 pulses at 484.28 kHz

(fC/28) as shown in Figure 33. For the Fast commands, the x2 mode is not available.

Figure 33.

Logic 0, low data rate

A logic 1 starts with 36 pulses at 484.28 kHz (fC/28) followed by 32 pulses at 423.75 kHz

(fC/32) as shown in Figure 34. For the Fast commands, the x2 mode is not available.

Figure 34.

Logic 1, low data rate

37.46µs

ai12074

37.46µs

ai12073

149.84µs

ai12072

149.84µs

ai12075

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