LPC3131 datasheet(12/68 Pages) NXP

12 / 68 page

LPC3130_3131_1

Preliminary data sheet

Rev. 1 — 9 February 2009

12 of 68

NXP Semiconductors

LPC3130/3131

Low-cost, low-power ARM926EJ-S microcontrollers

[1]

When the SDRAM is used, the supply voltage of the NAND ﬂash, SDRAM, and the LCD Interface must be the same, i.e. SUP4 and

SUP8 should be connected to the same rail. (See also Section 6.26.3.)

Table 5.

Supply domains

Supply

Domain

Voltage range

Related supply pins

Description

SUP1

1.0 V– 1.3 V

VDDI, VDDA12, USB_VDDA12_PLL, Digital core supply

SUP3

2.7 V - 3.3 V

VDDE_IOC, ADC10B_VDDA33,

USB_VDDA33_DRV, USB_VDDA33,

Peripheral supply

SUP4

1.65 V - 1.95 V (in 1.8 V

mode)

2.5 V - 3.1 V (in 2.8 V mode)

VDDE_IOA

Peripheral supply for NAND ﬂash

interface

SUP5

4.5 V– 5.5 V

USB_VBUS

USB VBUS voltage

SUP8

1.65 V - 1.95 V (in 1.8 V

mode)

2.5 V - 3.1 V (in 2.8 V mode)

VDDE_IOB

Peripheral supply for

SDRAM/SRAM/bus-based LCD [1]

Table 6:

I/O pads

Cell type

Pad type

Function

Description

DIO1

bspts3chp

Digital Input/Output

Bidirectional 3.3 V; 3-state output; 3 ns slew rate control; plain

input; CMOS with hysteresis; programmable pull-up, pull-down,

repeater

DIO2

bpts5pcph

Digital Input/Output

Bidirectional 5 V; plain input; 3-state output; CMOS with

programmable hysteresis; programmable pull-up, pull-down,

repeater

DIO4

mem1

bsptz40pchp

Digital Input/Output

Bidirectional 1.8 V or 2.8 V; plain input; 3-state output;

programmable hysteresis; programmable pull-up, pull-down,

repeater

IICC

iic3m4scl

Digital Input/Output

I2C-bus; clock signal

IICD

iic3mvsda

Digital Input/Output

I2C-bus; data signal

AIO1

apio3v3

Analog Input/Output Analog input/output; protection to external 3.3 V supply rail

AIO2

apio

Analog Input/Output Analog input/output

AIO3

apiot5v

Analog Input/Output Analog input/output; 5 V tolerant pad-based ESD protection

CS1

vddco

Core Supply

CS2

vddi

Core Supply

PS1

vdde3v3

Peripheral Supply

PS2

vdde

Peripheral Supply

CG1

vssco

Core Ground

CG2

vssis

Core Ground

PG1

vsse

Peripheral Ground

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