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LPC2888 bảng dữ liệu(PDF) 21 Page - NXP Semiconductors

tên linh kiện LPC2888
Giải thích chi tiết về linh kiện  16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
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LPC2888 bảng dữ liệu(HTML) 21 Page - NXP Semiconductors

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LPC2880_LPC2888_3
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 03 — 17 April 2008
21 of 43
NXP Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• Supports normal (100 kHz) and fast (400 kHz) operation.
6.16 10-bit ADC
The LPC2880/2888 contains a single 10-bit successive approximation ADC with five
multiplexed channels.
6.16.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 5 pins.
• Power-down mode.
• Measurement range 0 V to 3.3 V.
• 10-bit conversion time
≥ 2.44 µs.
• Single or continuous conversion mode.
6.17 Analog I/O
The analog I/O system includes an I2S-bus input channel, an I2S-bus output channel, a
dual ADC, and a dual DAC. Each channel includes a separate 4-sample FIFO.
Each of the two ADC inputs is connected to a Programmable Gain Amplifier (PGA).
Each DAC has two output pins.
6.17.1 Features
• I2S-bus input channel with a 4-sample FIFO for stereo DAI.
• I2S-bus output channel with a 4-sample FIFO for stereo DAO.
• Dual 16-bit ADCs with individual inputs routed through programmable gain amplifiers.
Input takes place through a 4-sample FIFO.
• Dual 16-bit DACs. Each DAC has its own output pin. Output takes place through a
4-sample FIFO.
6.18 USB 2.0 Hi-Speed device controller
The USB is a 4-wire bus that supports communication between a host and a number (127
maximum) of peripherals. The host controller allocates the USB bandwidth to attached
devices through a token based protocol. The bus supports hot plugging, un-plugging and
dynamic configuration of the devices. All transactions are initiated by the host controller.
The host schedules transactions in 1 ms frames. Each frame contains an SOF marker and
transactions that transfer data to/from device endpoints. There are four types of transfers
defined for the endpoints. Control transfers are used to configure the device. Interrupt
transfers are used for periodic data transfer. Bulk transfers are used when rate of transfer
is not critical. Isochronous transfers have guaranteed delivery time but no error correction.



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