TAS5612APHD datasheet(3/26 Pages) TI

3 / 26 page

TAS5612A

www.ti.com

SLAS710 – JUNE 2010

MODE SELECTION PINS

MODE PINS

OUTPUT

PWM INPUT(1)

DESCRIPTION

CONFIGURATION

2 × BTL

AD mode

—

Reserved

2 × BTL

BD mode

1 × BTL +2 ×SE

AD mode

4 × SE

AD mode

INPUT_C(2)

INPUT_D(2)

1 × PBTL

AD mode

BD mode

Reserved

(1)

The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.

(2)

INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode

PACKAGE HEAT DISSIPATION RATINGS

(1)

PARAMETER

TAS5612APHD

TAS5612ADKD

RqJC (°C/W) – 2 BTL or 4 SE channels

3.2

2.1

RqJC (°C/W) – 1 BTL or 2 SE channel(s)

5.4

3.5

RqJC (°C/W) – 1 SE channel

7.9

5.1

Pad Area (2)

64mm2

80mm2

(1)

JC is junction-to-case, CH is case-to-heat sink

(2)

RqCH is an important consideration. Assume a 2-mil thickness of thermal grease with a thermal conductivity of 2.5 W/mK between the

pad area and the heat sink and both channels active. The RqCH with this condition is 1.1°C/W for the PHD package and 0.44°C/W for

the DKD package.

Table 1. ORDERING INFORMATION(1)

PACKAGE

DESCRIPTION

0°C–70°C

TAS5612APHD

64 pin HTQFP

0°C–70°C

TAS5612ADKD

44 pin PSOP3

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Submit Documentation Feedback

Product Folder Link(s): TAS5612A

TAS5612APHD bảng dữ liệu(PDF) 3 Page - Texas Instruments

TAS5612APHD bảng dữ liệu(HTML) 3 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

bảng dữ liệu tải về

Link URL