LPC1759 datasheet(36/64 Pages) NXP

36 / 64 page

LPC1759_58_56_54_52_51_4

Product data sheet

Rev. 04 — 26 January 2010

36 of 64

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

7.30.5 AHB multilayer matrix

The LPC1759/58/56/54/52/51 use an AHB multilayer matrix. This matrix connects the

instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash

memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access

all of these memories. The peripheral DMA controllers, Ethernet (LPC1758 only) and

USB, can access all SRAM blocks. Additionally, the matrix connects the CPU system bus

and all of the DMA controllers to the various peripheral functions.

7.30.6 External interrupt inputs

The LPC1759/58/56/54/52/51 include up to 30 edge sensitive interrupt inputs combined

with one level sensitive external interrupt input as selectable pin function. The external

interrupt input can optionally be used to wake up the processor from Power-down mode.

7.30.7 Memory mapping control

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address

space. The vector table must be located on a 128 word (512 byte) boundary because the

NVIC on the LPC1759/58/56/54/52/51 is configured for 128 total interrupts.

7.31 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four

watch points.

LPC1759 bảng dữ liệu(PDF) 36 Page - NXP Semiconductors