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tên linh kiện CDCE62005RGZR
Giải thích chi tiết về linh kiện  Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
PDF  80 Pages
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Trang chủ  http://www.ti.com
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CDCE62005RGZR bảng dữ liệu(HTML) 1 Page - Texas Instruments

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CDCE62005
www.ti.com
SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010
Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
Check for Samples: CDCE62005
1
FEATURES
•
Frequency Synthesizer With PLL/VCO and
–
Independent Coarse Skew Control on all
Partially Integrated Loop Filter.
Outputs, The coarse skew control does not
operate for reference input frequencies less
•
Fully Configurable Outputs Including
than 1 MHz
Frequency, Output Format, and Output Skew.
•
Flexible Inputs With Innovative Smart
•
Smart Input Multiplexer Automatically
Multiplexer Feature:
Switches Between One of Three Reference
Inputs.
–
Two Universal Differential Inputs Accept
Frequencies in the Range of 40 kHz to
•
Multiple Operational Modes Include Clock
1500 MHz (LVPECL), 800 MHz (LVDS), or
Generation via Crystal, SERDES Startup Mode,
250 MHz (LVCMOS).
Jitter Cleaning, and Oscillator Holdover Mode
–
One Auxiliary Input Accepts Crystals in the
•
Integrated EEPROM Determines Device
Range of 2 MHz–42 MHz
Configuration at Power-up
–
Clock Generator Mode Using Crystal Input.
•
Excellent Jitter Performance
–
Smart Input Multiplexer can be Configured
•
Integrated Frequency Synthesizer including
to Automatically Switch Between Highest
PLL, Multiple VCOs, and Loop Filter:
Priority Clock Source Available Allowing
–
Full Programmability Facilitates Phase
for Fail-safe Operation and Holdover
Noise Performance Optimization Enabling
Modes.
Jitter Cleaner Mode.
•
Typical Power Consumption 1.7W (See
–
Programmable Charge Pump Gain and
Table 44) at 3.3V
Loop Filter Settings
•
Integrated EEPROM Stores Default Settings;
–
Unique Dual-VCO Architecture Supports a
Therefore, The Device Can Power up in a
Wide Tuning Range 1.750 GHz–2.356 GHz
Known, Predefined State.
•
Universal Output Blocks Support up to 5
•
Offered in QFN-48 Package
Differential, 10 Single-ended, or Combinations
•
ESD Protection Exceeds 2kV HBM
of Differential or Single-ended:
•
Industrial Temperature Range –40°C to 85°C
–
0.35 ps RMS (10 kHz to 20 MHz) Output
Jitter Performance
APPLICATIONS
–
Low Output Phase Noise: –130 dBc/Hz at 1
•
Data Converter and Data Aggregation Clocking
MHz offset, Fc = 491.52 MHz
•
Wireless Infrastructure
–
Output Frequency Ranges From 4.25 MHz
•
Switches and Routers
to 1.175 GHz in Synthesizer Mode
•
Medical Electronics
–
Output Frequency up to 1.5 GHz in Fan-out
•
Military and Aerospace
Mode
•
Industrial
–
LVPECL, LVDS, LVCMOS, and Special High
•
Clock Generation and Jitter Cleaning
Output Swing Modes
–
Independent Output Dividers Support
Divide Ratios from 1–80, Non-continuous
values supported.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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