ISO721 datasheet(7/26 Pages) TI

7 / 26 page

ISO721, ISO721M

ISO722, ISO722M

www.ti.com

SLLS629I – JANUARY 2006 – REVISED FEBRUARY 2010

ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V

(1) OPERATION

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Quiescent

0.3

0.5

ICC1

VCC1 supply current

VI = VCC or 0 V, No load

25 Mbps

ISO722/722M

EN at VCC

200

Sleep Mode

VI = VCC or 0 V,

No load

ICC2

VCC2 supply current

EN at 0 V or

Quiescent

ISO721/721M

25 Mbps

VI = VCC or 0 V, No load

IOH = –4 mA, See Figure 1

VCC – 0.8

4.6

VOH

High-level output voltage

IOH = –20 mA, See Figure 1

VCC – 0.1

IOL = 4 mA, See Figure 1

0.2

0.4

VOL

Low-level output voltage

IOL = 20 mA, See Figure 1

0.1

VI(HYS) Input voltage hysteresis

150

IIH

High-level input current

EN, IN at 2 V

IIL

Low-level input current

EN, IN at 0.8 V

–10

High-impedance output

IOZ

ISO722, ISO722M

EN, IN at VCC

current

Input capacitance to ground

IN at VCC, VI = 0.4 sin (4E6pt)

CMTI

Common-mode transient immunity

VI = VCC or 0 V, See Figure 5

kV/ms

(1)

For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.

SWITCHING CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V OPERATION

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH

Propagation delay, low-to-high-level output

tPHL

Propagation delay , high-to-low-level output

ISO72x

tsk(p)

Pulse skew |tPHL – tPLH|

0.5

EN at 0 V,

See Figure 1

tPLH

Propagation delay, low-to-high-level output

tPHL

Propagation delay, high-to-low-level output

ISO72xM

tsk(p)

Pulse skew |tPHL – tPLH|

0.5

tsk(pp)

(1)

Part-to-part skew

Output signal rise time

EN at 0 V,

See Figure 1

Output signal fall time

Sleep-mode propagation delay,

tpHZ

high-level-to-high-mpedance output

See Figure 2

Sleep-mode propagation delay,

tpZH

4.5

high-impedance-to-high-level output

ISO722

ISO722M

Sleep-mode propagation delay,

tpLZ

low-level-to-high-impedance output

See Figure 3

Sleep-mode propagation delay,

tpZL

4.5

high-impedance-to-low-level output

tfs

Failsafe output delay time from input power loss

See Figure 4

100 Mbps NRZ data input, See Figure 6

ISO72x

100 Mbps unrestricted bit run length data

input, See Figure 6

tjit(PP)

Peak-to-peak eye-pattern jitter

150 Mbps NRZ data input, See Figure 6

ISO72xM 150 Mbps unrestricted bit run length data

input, See Figure 6

(1)

tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

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Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M

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