| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
CS4294/CS4298 bảng dữ liệu(PDF) 20 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS4294/CS4298 bảng dữ liệu(HTML) 20 Page - Cirrus Logic |
|
20 / 66 page ![]() CS4202 20 DS549PP2 3.3 AC-Link Protocol Violation - Loss of SYNC The CS4202 is designed to handle SYNC protocol violations. The following are situations where the SYNC protocol has been violated: • The SYNC signal is not sampled high for exact- ly 16 BIT_CLK clock cycles at the start of an audio frame. • The SYNC signal is not sampled high on the 256th BIT_CLK clock period after the previous SYNC assertion. • The SYNC signal goes active high before the 256th BIT_CLK clock period after the previous SYNC assertion. Upon loss of synchronization with the controller, the CS4202 will ‘clear’ the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the CS4202 will ignore all register reads and writes and will discontinue the transmission of PCM capture data. In addition, if the LOSM bit in the Misc. Crystal Control Register (Index 60h) is ‘set’ (default), the CS4202 will mute all analog outputs. If the LOSM bit is ‘clear’, the analog outputs will not be muted. |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |