CS49310 datasheet(22/90 Pages) CIRRUS

22 / 90 page

CS49300 Family DSP

DS339F7

1.15. Switching Characteristics — Digital Audio Output

(VA, VD[3:1] = 2.5 V

±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 1. MCLK can be an input or an output. These specifications apply for both cases.

2. Master mode timing specifications are characterized, not production tested.

3. Master mode is defined as the CS493XX driving both SCLK and LRCLK. When MCLK is an input, it is

divided to produce SCLK and LRCLK.

4. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the

point at which the data is valid.

5. Slave mode is defined as SCLK and LRCLK being driven by an external source.

6. This specification is characterized, not production tested.

Parameter

Symbol

Min

Max

Unit

MCLK period

(Note 1)

Tmclk

MCLK duty cycle

(Note 1)

SCLK period for Master or Slave mode

(Note 2)

Tsclk

SCLK duty cycle for Master or Slave mode

(Note 2)

Master Mode

(Note 2, 3)

SCLK delay from MCLK rising edge, MCLK as an input

Tsdmi

SCLK delay from MCLK rising edge, MCLK as an output

Tsdmo

–5

LRCLK delay from SCLK transition

(Note 4)

Tlrds

AUDATA2–0 delay from SCLK transition

(Note 4)

Tadsm

Slave Mode

(Note 5)

Time from active edge of SCLKN1(2) to LRCLKN1(2) transition

Tstlr

Time from LRCLKN1(2) transition to SCLKN1(2) active edge

Tlrts

AUDATA2–0 delay from SCLK transition

(Note 4, 6)

Tadss

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