TMP320C6727BRFP300 datasheet(13/118 Pages) TI

13 / 118 page

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

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SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

The five bus masters arbitrate for five different target groups:

On-chip memories through the CPU Slave Port (CSP).

Memories on the external memory interface (EMIF).

Peripheral registers through the peripheral configuration bus.

McASP serializers through the dedicated McASP DMA bus.

dMAX registers.

The crossbar switch supports parallel accesses from different bus masters to different targets. When two

or more bus masters contend for the same target beginning at the same cycle, then the highest-priority

master is given ownership of the target while the other master(s) are stalled. However, once ownership of

the target is given to a bus master, it is allowed to complete its access before ownership is arbitrated

again. Following are two examples.

Example 1: Simultaneous accesses without conflict

• dMAX HiMAX accesses McASP Data Port for transfer of audio data.

• dMAX LoMAX accesses SPI port for control processing.

• UHPI accesses internal RAM through the CSP.

• CPU fills program cache from EMIF.

Example 2: Conflict over a shared resource

• dMAX HiMAX accesses RTI port for McASP sample rate measurement.

• dMAX LoMAX accesses SPI port for control processing.

In Example 2, both masters contend for the same target, the peripheral configuration bus. The HiMAX

access will be given priority over the LoMAX access.

The master priority is illustrated in Figure 2-4 by the numbers 1 through 4 in the bus arbiter symbols. Note

that the EMIF arbitration is distributed so that only one bridge crossing is necessary for PMP accesses.

The effect is that PMP has 5th priority to the EMIF but lower latency.

A bus bridge is needed between masters and targets which run at different clock rates. The bus bridge

contains a small FIFO to allow the bridge to accept an incoming (burst) access at one clock rate and pass

it through the bridge to a target running at a different rate. Table 2-6 lists the FIFO properties of the four

bridges (BR1, BR2, BR3, and BR4) in Figure 2-4.

Table 2-6. Bus Bridges

LABEL

BRIDGE DESCRIPTION

MASTER CLOCK

TARGET CLOCK

BR1

DMP Bridge to peripherals, dMAX, EMIF

SYSCLK1

SYSCLK2

BR2

dMAX, UHPI to ROM/RAM (CSP)

SYSCLK2

SYSCLK1

BR3

PMP to EMIF

SYSCLK1

SYSCLK3

BR4

CPU, UHPI, and dMAX to EMIF

SYSCLK2

SYSCLK3

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