MIC2829 datasheet(30/52 Pages) MICREL

30 / 52 page

Micrel Inc.

MIC2829

May 2010

M9999-051410-B

Functional Description

AVIN1 and AVIN2

The input supply pins (AVIN1 and AVIN2) provide bias to

the internal LDO circuitry and the input voltage to LDO1

and LDO11. The AVIN operating range is 2.7V to 5.5V

so a minimum 1µF input capacitor with a 6.3V voltage

rating placed as close to the AVIN and ground (AGND1

and AGND2) is required. Capacitance decreases as the

DC bias across the capacitor increases and should be

considered when selecting a suitable capacitor. AVIN1

and AVIN2 are internally connected. All AVINs should be

tied together and connected to the PVINs of the device.

Refer to the layout recommendations for details.

AVIN3 and AVIN4

The input supply pins (AVIN3 and AVIN4) provide bias to

the internal circuitry for the switch mode regulators (DC1

through DC6) and power to SIMPWR. The AVIN

operating range is 2.7V to 5.5V, so a minimum 1µF input

capacitor with a minimum voltage rating of 6.3V placed

close to AVIN and ground (AGND3 and AGND4) is

required. AVIN3 and AVIN4 are internally connected. All

AVINs should be tied together and connected to the

PVINs

the

device.

Refer

the

layout

recommendations for details.

PVIN1 to PVIN6

The power input supply pins (PVIN1 to PVIN6) provide

power to the switch mode regulators (DC1 to DC6). Due

to high switching currents, a minimum 1µF input

capacitor with a minimum voltage rating of 6.3V placed

close to PVIN and the power ground is required. The

PVIN tracks should be as wide as possible and the 1µF

capacitor should be placed from PVIN1 to PGND1 due

to the proximity of their pin location. The same should be

done with each PVIN and PGND combination. All AVINs

should be tied together and connected to the PVINs of

the device. Refer to the layout recommendations for

details.

AGND1 and AGND2

The ground pins (AGND1 and AGND2) are the ground

path for the biasing, the control circuitry and the power

ground for all LDOs. AGND1 and AGND2 are internally

connected. The current loop for the ground should be

kept as short as possible. Connect AGND1 and AGND2

together. Refer to the layout recommendations for more

details.

AGND3 and AGND4

The analog ground pins (AGND3 and AGND4) are the

ground path for the biasing and the control circuitry for

all buck regulators. This is a low current ground path and

should not be mixed with high current paths such as

PGND. To reduce the effects of parasitic interference in

the layout, AGND3 should be connected to the PGND

plane near the PGND3 pin. Similarly, AGND4 should be

connected to the PGND plane near the PGND4 pin. This

allows the AGND3 and AGND4 ground voltage to be as

close to the PGND ground voltage as possible. Should

the AGND3 and AGND4 connect further from the

PGND3 and PGND4 pins, then the effects of parasitic

inductance

and

resistance

would

reduce

the

performance by altering the accuracy of ground. Refer to

the layout recommendations for more details.

PGND1 to PGND6

The power ground pins (PGND1 to PGND6) are the

ground path for the high current ground path for DC1

through DC6. The current loop for the power ground

should be as small as possible and separate from the

analog ground (AGND3, AGND4) loop. All power

grounds (PGND1 to PGND6) should be connected on

the same plane. Refer to the layout recommendations

for more details.

INLDO

The

INLDO

pins

(INLDO23,

INLDO45,

INLDO6,

INLDO7, INLDO8, and INLDO910) are the power input

for the respective LDOs. Due to line inductance, a

minimum of 1µF input capacitor with a minimum voltage

rating of 6.3V should be placed as close as possible to

the INLDO pin and ground (AGND1, AGND2). Refer to

the layout recommendations for more details.

LDO

The LDO pins (LDO1 to LDO11) are the output of the

LDO and LNR regulators. For LDO1, LDO2, LDO3,

LDO4 and LDO11, a minimum of 1µF output capacitor

with a minimum voltage rating of 6.3V placed as close to

the LDO pin and ground (AGND1 and AGND2) as

possible is required. For the LNRs (LDO5 to LDO10), a

2.2µF output capacitor with a minimum voltage rating of

6.3V placed as close as possible to the LDO pin and

ground (AGND1 and AGND2) is recommended. Refer to

the layout recommendations for more details.

BYP

The reference bypass pin (BYP) acts as a filter for the

reference voltage of LNR5 to LNR10. A 0.1µF bypass

capacitor connected to ground (AGND1 and AGND2) is

recommended.

SUB

The SUB pin (SUB1, SUB2) is connected internally to

the guard ring ground protection. The guard ring

prevents interaction between regulators inside the die

package. Connect SUB1 and SUB2 pins to ground

(AGND1, AGND2) externally.

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