74LVC595A_1

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 01 — 29 May 2007

12 of 19

NXP Semiconductors

74LVC595A

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Measurement points are given in Table 8.

Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the

master reset to shift clock (SHCP) recovery time

mna561

MR input

SH

CP input

Q

7S output

GND

GND

Measurement points are given in Table 8.

Fig 12. 3-state enable and disable times

001aae821

outputs

disabled

outputs

enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input

GND

GND

Table 8.

Measurement points

Supply voltage

Input

Output

0.5

× V

CC

0.5

× V

CC

1.5 V

1.5 V