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74LVC2G240DP bảng dữ liệu(PDF) 2 Page - NXP Semiconductors |
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74LVC2G240DP bảng dữ liệu(HTML) 2 Page - NXP Semiconductors |
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2 / 16 page ![]() 74LVC2G240_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 29 February 2008 2 of 16 NXP Semiconductors 74LVC2G240 Dual inverting buffer/line driver; 3-state 3. Ordering information 4. Marking 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G240DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G240DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74LVC2G240GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 74LVC2G240GM −40 °C to +125 °C XQFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm SOT902-1 Table 2. Marking codes Type number Marking code 74LVC2G240DP V240 74LVC2G240DC V40 74LVC2G240GT V40 74LVC2G240GM V40 Fig 1. Logic symbol Fig 2. IEC logic symbol 001aah782 1A 2Y 1Y 1OE 2A 2OE EN EN 001aah783 |
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